Syntor-X Code Plug Layout (or "You don't need the Suitcase Programmer")
Thanks to Mike Blenderman, K7IC, for filling in many of the blank fields.

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Sample Programming Sheet

A QBASIC Program to generate PROM data for the Low Band Syntor X contributed by Brian Ellsworth, KA1JY

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The Syntor-X code plug contains a generic standard 2816-type 2Kx8 EEPROM. The 2816 can be read and written using virtually any standard EPROM programmer.

Each mode is specified by 16 bytes, starting with mode 1 at address $0000. Thus, mode 1 is contained in addresses 0000 through 000F, mode 2 in addresses 0010-001F, etc. There are a total of 32 entries for up to 32 modes. The modes account for 512 bytes of the EEPROM. The second 512 byte block contains optional Operator Select Coded Squelch codes (MPL). The EEPROM address lines are hooked up to access only 1024 bytes of the total 2048 bytes so these two 512 byte blocks account for all the usable space in the code plug.

(H Nibble = D₇D₆D₅D₄ L Nibble=D₃D₂D₁D₀)

Byte	Nibble	Field	Function
0	H	M1M2M3M4	Channel Scan non-priority scan list
0	L	M5M6M7M8	Channel Scan non-priority scan list
1	H	M9M10M11M12	Channel Scan non-priority scan list
1	L	M13M14M15M16	Channel Scan non-priority scan list
2	H	M17M18M19M20	Channel Scan non-priority scan list
2	L	M21M22M23M24	Channel Scan non-priority scan list
3	H	M25M26M27M28	Channel Scan non-priority scan list
3	L	M29M30M31M32	Channel Scan non-priority scan list
4	H	XP7XP6XP5XP4	Transmit PL / DPL / Disable
4	L	XP3XP2XP1XP0	Transmit PL / DPL / Disable
5	H	XM0XS0XP13XP12	Transmit PL / DPL / Disable
5	L	XP11XP10XP9XP8	Transmit PL / DPL / Disable
6	H	RP7RP6RP5RP4	Receive PL / DPL / Disable
6	L	RP3RP2RP1RP0	Receive PL / DPL / Disable
7	H	RM0RS0RP13RP12	Receive PL / DPL / Disable
7	L	RP11RP10RP9RP8	Receive PL / DPL / Disable
8	H	T4T3T2T1	Time-out
8	L	T0X0CR0	Time-out, Power control, Ref. Freq.
9	H	ST1ST0TB0P24	Scan Control
9	L	P23P22P21P20	Scan Control
A	H	SS0SQ1SQ0P14	Scan Control and Squelch Control
A	L	P13P12P11P10	Scan Control and Squelch Control
B	H	V1V0C1C0	Tx synthesizer program address 6
B	L	V1V0C1C0	Rx synthesizer program address 6
C	H	B9B8B7B6	Tx synthesizer program address 4
C	L	B9B8B7B6	Rx synthesizer program address 4
D	H	B5B4B3B2	Tx synthesizer program address 3
D	L	B5B4B3B2	Rx synthesizer program address 3
E	H	B1B0A5A4	Tx synthesizer program address 1
E	L	B1B0A5A4	Rx synthesizer program address 1
F	H	A3A2A1A0	Tx synthesizer program address 0
F	L	A3A2A1A0	Rx synthesizer program address

Bytes 0, 1, 2, 3 - Channel Scan non-priority internal list. Any bit set to a zero will include the corresponding mode in the non-priority scan list. 0xFFFFFFFF is an empty non-priority scan list.

	Byte 0:	Byte 1:	Byte 2:	Byte 3:
D7	- mode 1	- mode 9	- mode 17	- mode 25
D6	- mode 2	- mode 10	- mode 18	- mode 26
D5	- mode 3	- mode 11	- mode 19	- mode 27
D4	- mode 4	- mode 12	- mode 20	- mode 28
D3	- mode 5	- mode 13	- mode 21	- mode 29
D2	- mode 6	- mode 14	- mode 22	- mode 30
D1	- mode 7	- mode 15	- mode 23	- mode 31
D0	- mode 8	- mode 16	- mode 24	- mode 32

• When Selectable Scan is enabled the radio will not use the above scan list. Fixed Scan must be enabled to use this scan list (see Byte A details).

Bytes 4, 5 - Tx PL / DPL / Disable codes. 0xFFDF is PL/DPL Disabled with no MPL Select (0x00C0 also works).

Tx and Rx DPL Codes (A2A1A0) (B2B1B0) (C2C1C0)
NOR	INV	NOR	INV	NOR	INV	NOR	INV	NOR	INV
023	047	116	754	244	025	411	226	612	346
025	244	125	365	245	072	412	143	624	632
026	464	131	364	251	165	413	054	627	031
031	627	132	546	261	732	423	315	631	606
032	051	134	223	263	205	431	723	632	624
036	172	143	412	265	156	432	516	654	743
043	445	152	115	271	065	445	043	662	466
047	023	155	731	306	071	464	026	664	311
051	032	156	265	311	664	465	331	703	565
054	413	162	503	315	423	466	662	712	114
065	271	165	251	331	465	503	162	723	431
071	306	172	036	343	532	506	073	731	155
072	245	174	074	346	612	516	432	732	261
073	506	205	263	351	243	532	343	734	371
074	174	223	134	364	131	546	132	743	654
114	712	226	411	365	125	565	703	754	116
115	152	243	351	371	734	606	631

• NOR - Normal DPL codes.
• INV - Inverted DPL codes (this is a result of the DPL signal inversion, not a logical bit inversion).
• All 9 bit values are logically inverted. i.e. DPL 023 would be stored as 754, or 047 would be 730.
• There are 84 standard DPL codes.
• DPL codes are exactly the same format for Tx and Rx. Use this table for Rx DPL also.

Tx PL Codes and Control Bits PL - byte 4,5 (P7 - P0, M=1, S=0, P13 - P8)
67.0 (XZ) - 0x45BB	97.4 (ZB) - 0x20B9	141.3 (4A) - 0x07B6	206.5 (8Z) - 0x6EB1
69.3 (WZ) - 0x1CBB	100.0 (1Z) - 0xF1B8	146.2 (4B) - 0xAFB5	210.7 (M2) - 0x22B1
71.9 (XA) - 0xEDBA	103.5 (1A) - 0xB2B8	151.4 (5Z) - 0x51B5	218.1 (M3) - 0x9CB0
74.4 (WA) - 0xC0BA	107.2 (1B) - 0x6FB8	156.7 (5A) - 0xF1B4	225.7 (M4) - 0x13B0
77.0 (XB) - 0x91BA	110.9 (2Z) - 0x2CB8	162.2 (5B) - 0x8EB4	229.1 (9Z) - 0xD6AF
79.7 (WB) - 0x60BA